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16-Mbit (2M x 8) MoBL Static RAM
Features
CY62168DV30 MoBL(R) (R)
Very high speed 55 ns Wide voltage range 2.2 V - 3.6 V Ultra-low active power Typical active current: 2 mA @ f = 1 MHz Typical active current: 15 mA @ f = fMax (55 ns Speed) Ultra-low standby power Easy memory expansion with CE1, CE2 and OE features Automatic power-down when deselected Complementary metal oxide semiconductor (CMOS) for optimum speed/power Available in non Pb-free 48-ball very fine ball grid array (VFBGA) package.
automatic power-down feature that significantly reduces power consumption. The device can be put into standby mode reducing power consumption by 90% when addresses are not toggling. The device can be put into standby mode reducing power consumption by more than 99% when deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW. The input/output pins (I/O0 through I/O7) are placed in a high-impedance state when: deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW, outputs are disabled (OE HIGH), or during a write operation (Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and WE LOW). Writing to the device is accomplished by taking Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and Write Enable (WE) input LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins(A0 through A20). Reading from the device is accomplished by taking Chip Enable 1 (CE1) and Output Enable (OE) LOW and Chip Enable 2 (CE2) HIGH while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 LOW and CE2 HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW and CE2 HIGH and WE LOW). See the "Truth Table" on page 10 for a complete description of read and write modes.

Functional Description[1]
The CY62168DV30 is a high-performance CMOS static RAMs organized as 2048Kbit words by 8 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery LifeTM (MoBL(R)) in portable applications such as cellular telephones. The device also has an
Logic Block Diagram
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
CE1 CE2 WE OE
Data in Drivers
I/O0 I/O1
ROW DECODER
SENSE AMPS
I/O2 I/O3 I/O4 I/O5
2048K x 8 ARRAY
COLUMN DECODER
POWER DOWN
I/O6 I/O7
Note 1. For best-practice recommendations, please refer to the Cypress application note entitled System Design Guidelines, available at http://www.cypress.com.
Cypress Semiconductor Corporation Document Number : 38-05329 Rev. *I
*
198 Champion Court
A17 A18 A19 A20
A16
A13 A14 A15
*
San Jose, CA 95134-1709 * 408-943-2600 Revised November 19, 2010
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CY62168DV30 MoBL(R)
Contents
Pin Configuration .............................................................. 3 Product Portfolio .............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 DC Electrical Characteristics .......................................... 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 5 Data Retention Waveform ................................................ 6 Switching Characteristics ................................................ 7 Switching Waveforms ...................................................... 8 Truth Table ...................................................................... 10 Ordering Information ...................................................... 10 Ordering Code Definition ........................................... 10 Package Diagram ............................................................ 11 Acronyms ........................................................................ 11 Document Conventions ................................................. 11 Units of Measure ....................................................... 11 Document History Page ................................................. 12 Sales, Solutions, and Legal Information ...................... 13 Worldwide Sales and Design Support ....................... 13 Products .................................................................... 13 PSoC Solutions ......................................................... 13
Document Number : 38-05329 Rev. *I
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CY62168DV30 MoBL(R)
Pin Configuration[2]
48-ball VFBGA Top View
1 DNU 2 OE 3 A0 A3 A5 A17 DNU A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 6 CE2 A B C D E F G H
DNU DNU I/O0 VSS VCC I/O3 DNU A18 DNU I/O1 I/O2 DNU A20 A8
CE1 DNU DNU I/O5 I/O6 DNU WE A11 I/O4 VCC VSS I/O7 DNU A19
Product Portfolio
Power Dissipation Product Min CY62168DV30LL 2.2 VCC Range (V) Speed (ns) Max 3.6 55 Operating ICC (mA) f = 1 MHz Typ [3] 2 Max 4 f = fMax Typ[3] 15 Max 30 Standby ISB2(A) Typ[3] 2.5 Max 22
Typ[3] 3.0
Notes 2.DNU pins have to be left floating or tied to VSS to ensure proper operation. 3.Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 C.
Document Number : 38-05329 Rev. *I
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CY62168DV30 MoBL(R)
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage temperature................................. -65 C to +150 C Ambient temperature with power applied ........................................... -55 C to +125 C Supply voltage to ground potential ....................................... -0.3 V to VCC(max) + 0.3 V DC voltage applied to outputs in High-Z state[4, 5] .........................-0.3 V to VCC(max) + 0.3 V
DC input voltage[4, 5] ......................-0.3 V to VCC(max) + 0.3 V Output current into outputs (LOW) .............................. 20 mA Static discharge voltage........................................... > 2001 V (per MIL-STD-883, Method 3015) Latch-up current ..................................................... > 200 mA
Operating Range
Range Industrial Ambient Temperature (TA)[6] -40 C to +85 C VCC[7] 2.2 V - 3.6 V
DC Electrical Characteristics (Over the Operating Range)
Parameter VOH Description Output HIGH voltage Test Conditions 2.2 V < VCC < 2.7 V 2.7 V < VCC < 3.6 V VOL Output LOW voltage 2.2 V < VCC < 2.7 V 2.7 V < VCC < 3.6 V VIH Input HIGH voltage 2.2 V < VCC < 2.7 V 2.7 V < VCC < 3.6 V VIL Input LOW voltage 2.2 V < VCC < 2.7 V 2.7 V < VCC < 3.6 V IIX IOZ ICC Input leakage current Output leakage current GND < VI < VCC GND < VO < VCC, Output disabled VCC = 3.6 V, IOUT = 0 mA, CMOS level IOH = -0.1 mA IOH = -1.0 mA IOL = 0.1 mA IOL = 2.1 mA CY62168DV30-55 Min 2.0 2.4 - - 1.8 2.2 -0.3 -0.3 -1 -1 - - - Typ[8] - - - - - - - - - - 15 2 2.5 Max - - 0.4 0.4 VCC + 0.3 VCC + 0.3 0.6 0.8 +1 +1 30 4 22 A A A mA V V V Unit V
VCC operating supply current f = fMax = 1/tRC f = 1 MHz
ISB1
Automatic CE Power-down current -- CMOS inputs
CE1 > VCC - 0.2 V, CE2 < 0.2 V, VIN > VCC - 0.2 V, VIN < 0.2 V, f = fMax (Address and data only), f = 0 (OE, WE) CE1 > VCC - 0.2 V, CE2 < 0.2 V, VIN > VCC - 0.2 V or VIN < 0.2 V, f = 0, VCC = 3.6 V
ISB2
Automatic CE Power-down current-- CMOS inputs
-
2.5
22
A
Notes 4. VIL(min) = -2.0 V for pulse durations less than 20 ns. 5. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns. 6. TA is the "Instant-On" case temperature. 7. Full device AC operation assumes a 100 s ramp time from 0 to VCC(min) and 100 s wait time after VCC stabilization. 8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 C
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CY62168DV30 MoBL(R)
Capacitance
Parameter[9] CIN COUT Description Input capacitance Output capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = VCC(typ.) Max 8 10 Unit pF pF
Thermal Resistance
Parameter[9] JA JC Description Thermal resistance (Junction to ambient) Thermal resistance (Junction to case) Test Conditions Still air, soldered on a 3 x 4.5 inch, 2-layer printed circuit board VFBGA 55 16 Unit C / W C / W
AC Test Loads and Waveforms
VCC OUTPUT 50 pF INCLUDING JIG AND SCOPE R2 R1 ALL INPUT PULSES VCC GND 10% 90% 90% 10%
Fall time: 1 V/ns
Rise Time: 1 V/ns
Equivalent to:
THEVENIN EQUIVALENT RTH VTH
OUTPUT
Parameters R1 R2 RTH VTH
2.5 V 16600 15400 8000 1.2
3.0 V 1103 1554 645 1.75
Unit V
Data Retention Characteristics (Over the Operating Range)
Parameter VDR ICCDR Description VCC for data retention Data retention current VCC = 1.5 V CE1 > VCC - 0.2 V or CE2 <0.2 V VIN > VCC - 0.2 V or VIN < 0.2 V tCDR[9] tR[11] Chip deselect to data retention time Operation recovery time 0 55 - - - - ns ns Conditions Min 1.5 - Typ[10] - - Max 3.6 10 Unit V A
Notes 9. Tested initially and after any design or process changes that may affect these parameters. 10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 C 11. Full Device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s..
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CY62168DV30 MoBL(R)
Data Retention Waveform
DATA RETENTION MODE VCC CE1 VCC(min) tCDR VDR > 1.5 V VCC(min) tR
or
CE2
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CY62168DV30 MoBL(R)
Switching Characteristics Over the Operating Range
Parameter[12] Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write Cycle[15] tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Write cycle time CE1 LOW and CE2 HIGH to write end Address set-up to write end Address hold from write end Address set-up to write start WE Pulse width Data set-up to write end Data hold from write end WE LOW to High Z[13, 14] WE HIGH to Low Z[13] 55 40 40 0 0 40 25 0 - 10 - - - - - - - - 20 - ns ns ns ns ns ns ns ns ns ns Read cycle time Address to data valid Data hold from address change CE1 LOW and CE2 HIGH to data valid OE LOW to data valid OE LOW to Low Z[13] OE HIGH to High Z[13, 14] CE1 LOW and CE2 HIGH to Low Z[13] CE1 HIGH or CE2 LOW to High Z[13, 14] CE1 LOW and CE2 HIGH to Power-up CE1 HIGH or CE2 LOW to Power-down 55 - 10 - - 5 - 10 - 0 - - 55 - 55 25 - 20 - 20 - 55 ns ns ns ns ns ns ns ns ns ns ns Description 55 ns Min. Max. Unit
Notes 12. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3ns or less (1V/ns), timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in the "AC Test Loads and Waveforms" section. 13. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 14. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state. 15. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
Document Number : 38-05329 Rev. *I
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CY62168DV30 MoBL(R)
Switching Waveforms
Figure 1. Read Cycle No. 1 (Address Transition Controlled)[16, 17]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Figure 2. Read Cycle No. 2 (OE Controlled)[17, 18]
ADDRESS tRC CE1 CE2 OE tDOE tLZOE HIGH IMPEDANCE DATA OUT VCC SUPPLY CURRENT tPU 50% tLZCE DATA VALID tPD 50%
tACE tHZOE tHZCE HIGH IMPEDANCE
ICC ISB
Figure 3. Write Cycle No. 1 (WE Controlled)[19, 20, 21]
tWC ADDRESS tSCE CE1
CE2 tAW tSA WE tPWE tHA
OE tSD DATA I/O tHD
See Note 22
tHZOE
VALID DATA
Notes 16. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 17. WE is HIGH for read cycle. 18. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH. 19. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. 20. Data I/O is high impedance if OE = VIH. 21. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high-impedance state. 22. During this period, the I/Os are in output state and input signals should not be applied.
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CY62168DV30 MoBL(R)
Switching Waveforms (continued)
Figure 4. Write Cycle No. 2 (CE1 or CE2 Controlled)[23, 24, 25]
tWC ADDRESS tSCE CE1 tSA CE2 tAW tPWE WE tHA
OE tSD DATA I/O VALID DATA tHD
Figure 5. Write Cycle No. 3 (WE Controlled, OE LOW)[26]
tWC ADDRESS tSCE CE1
CE2 tAW tSA WE tSD DATA I/O See Note 26 tHZWE VALID DATA tLZWE tHD tPWE tHA
Notes 23. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. 24. Data I/O is high impedance if OE = VIH 25. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high-impedance state. 26. During this period, the I/Os are in output state and input signals should not be applied
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CY62168DV30 MoBL(R)
Truth Table
CE1 H X L L L CE2 X L H H H WE X X H L H OE X X L X H Inputs/Outputs High Z High Z Data out (I/O0-I/O7) Data in (I/O0-I/O7) High Z Mode Deselect/Power-down Deselect/Power-down Read Write Output disabled Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at http://www.cypress.com and refer to the product summary page at http://www.cypress.com/products. Cypress maintains a worldwide network of offices, solution centers, manufacturers representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices. Speed (ns) 55 Ordering Code CY62168DV30LL-55BVI Package Diagram Package Type Operating Range Industrial
51-85178 48-ball Fine Pitch BGA (8 x 9.5 x 1 mm)
Please contact your local Cypress sales representative for availability of these parts
Ordering Code Definition
CY 621 6 8D V30 LL 55 XXX X
Tem perature Grades I = Industrial Package Type = BV: VFBGA Speed Grade Low Power Voltage = 3.0 Bus W idth = X8 D = 130nm Technology Density = 16 M bit M oBL SRAM Fam ily Com pany ID: CY = Cypress
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CY62168DV30 MoBL(R)
Package Diagram
51-85178 *A
Acronyms
Acronym CMOS I/O SRAM VFBGA TSOP input/output static random access memory very fine ball grid array thin small outline package Description complementary metal oxide semiconductor
Document Conventions
Units of Measure
Symbol C A mA MHz ns pF V W Unit of Measure degrees Celsius microamperes milliampere megahertz nanoseconds picofarads volts ohms watts
Document Number : 38-05329 Rev. *I
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CY62168DV30 MoBL(R)
Document History Page
Document Title: CY62168DV30 MoBL(R), 16-Mbit (2M x 8) MoBL(R) Static RAM Document Number: 38-05329 REV. ** *A *B *C *D *E *F ECN NO. 118409 123693 126556 132869 272589 335864 492895 Issue Date 09/30/02 02/05/03 04/24/03 01/15/04 See ECN See ECN See ECN Orig. of Change GUG DPM DPM XRJ PCI PCI VKN New Data Sheet Changed Advance Information to Preliminary Added package diagram Minor change: Change sunset owner from DPM to HRT Changed Preliminary to Final Updated Final data sheet and added Pb-free package. Removed redundant packages from Ordering Information Table Added Address A20 to ball G2 in the Pin Configuration Changed address of Cypress Semiconductor Corporation on Page# 1 from "3901 North First Street" to "198 Champion Court" Removed 70 ns speed bin Removed L power bin from product offering Updated Ordering Information Table Removed inactive part from Ordering Information. Updated Packaging Information Updated Template Added Acronyms and Units of Measure Added Ordering Code Definition Converted all tablenotes to footnote as per latest template Post to external web. Description of Change
*G *H
2914085 3070774
04/15/10 10/27/2010
NIKM RAME
*I
3090588
11/19/2010
AJU
Document Number : 38-05329 Rev. *I
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CY62168DV30 MoBL(R)
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.
Products
Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless
PSoC Solutions
psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5
(c) Cypress Semiconductor Corporation, 2002-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number : 38-05329 Rev. *I
Revised November 19, 2010
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MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document are trademarks of their respective holders
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